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Proceedings Paper

Shot number analysis on character projection e-beam lithography for random logic device fabrication at 70-nm node
Author(s): Yoichi Tomo; Isao Shimizu; Yoshinori Kojima; Akira Yoshida; Hiroshi Takenaka; Masaki Yamabe
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Paper Abstract

A reduction efficiency of shot numbers in character projection (CP) electron-beam (EB) lithography with memory device application depends on a design rule (cell size) and a pattern complexity within a memory cell. Many researchers reported that it was approximately 1/10 to 1/100 compared with conventional variable-shaped beam (VSB) method. The reduction of shot numbers in memory devices mainly comes from allowance to place multiple cells in one CP-cell area and simplicity of the cell's placement (regular pitch with adjacent allocation). On the other hand, there are few reports concerning reduction efficiency of shot numbers with logic specific application in CP EB lithography due to the complexity of logic cell's allocation to CP-cell area. To analyze this, logic device layout data in 70nm node was prepared by shringking actual functional device data of 350 nm node in the ratio of 1/5 and extracting random logic region. The size of this region was 1,094 x 283 micrometers . The height of logic cell was 2.64micrometers and it was smaller than typical one CP-cell size in second aperture (5 x 5micrometers ). The pattern data in GDS-II stream format was converted into EB exposure data: divided figures (rectangles). By this procedure, numbers of figures and cells were obtained. The total number of referred logic cell was 26,812. Among 26,812 cells, only 111 common (unique) logic cells were used for the logic region. The sum of figures in gate layer was 412,251 and this value was assumed to be equal to a total number of shots in conventional VSB method. Among the 111 common cells, only 6 cells in the gate layer showed width more than 5micrometers (maximum CP-cell size). Most frequently referred cell was an inverter and the number of reference was 5,395. The referred frequency of each cell exponentially decreased when the cells were arranged in descending order of reference. Among the total figures, top cell showed 66,120 accumulated number of figures (referred number=2,204, figures in cell=30). The cumulative number of total shots also exponentially decreased when cells were arranged in descending order of total shots. So it is necessary to decide the appropriate maximum number of CP- cell for futur CP EB exposure systems considering the reductoin efficiency of the shot numbers. For the current CP EB exposure tool of Hitachi (HL system), allowed number of CP-cell is 21 which means only 5 different (frequently referred) logic cells can be allocated in CP aperture with typical placement in 4 orientations. But even in this case, total required shot numbers of this logic region for EB Exposure can be reduced to approximately ½. For the ADVANEST CP EB system (allowed number of CP-cell = 100), reduction ratio of shot numbers is 1/4. For the pseudo CP EB system with 500 CP-cells in second aperture, reduction ratio of shot numbers would be 1/15. So, CP EB lithography is one of the promising candidates for small or medium volume production technology especially memory with logic device application after 70 nm node if the maximum number of CP-cell is appropriately increased.

Paper Details

Date Published: 20 August 2001
PDF: 12 pages
Proc. SPIE 4343, Emerging Lithographic Technologies V, (20 August 2001); doi: 10.1117/12.436694
Show Author Affiliations
Yoichi Tomo, Semiconductor Leading Edge Technologies, Inc. (Japan)
Isao Shimizu, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yoshinori Kojima, Semiconductor Leading Edge Technologies, Inc. (Japan)
Akira Yoshida, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroshi Takenaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Masaki Yamabe, Semiconductor Leading Edge Technologies, Inc. (Japan)

Published in SPIE Proceedings Vol. 4343:
Emerging Lithographic Technologies V
Elizabeth A. Dobisz, Editor(s)

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