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Proceedings Paper

Evaluating device design rules based on lithographic capability
Author(s): Scott P. Warrick; Chris J. Smith; Matt Monroe; Carroll Casteel; Mark Zaleski
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Paper Abstract

This paper demonstrates a method of analysis to determine a minimum achievable overlay design rule, for an existing stepper tool set in a high volume manufacturing fab. Overlay parameters and Critical Dimensions are considered in an overlay budget applying a modified algorithm to the evaluation of reticle errors, tool performance, and design rule analysis. The modified algorithm is used to determine the capability of an installed tool set of high NA steppers to meet the aggressive overlay requirements for advanced BiCMOS device performance. Design rule boundaries and tool set capability are thoroughly investigated. Experimental results from lithographic tests are used in a modified algorithm to determine the capability of running with current design rules or requiring a change for manufacturability. The impact of writing reticles to tighter specifications for both Critical Dimensions and pattern placement are considered. This study provides a method for chip designers and process engineers to determine the lithographic capability of an installed tool set where a part will eventually be fabricated. The results demonstrate that design rules demand optimum tool performance for overlay and CD control as well as provide a tool for the evaluation of continuous improvement.

Paper Details

Date Published: 14 September 2001
PDF: 8 pages
Proc. SPIE 4346, Optical Microlithography XIV, (14 September 2001); doi: 10.1117/12.435792
Show Author Affiliations
Scott P. Warrick, Motorola (United States)
Chris J. Smith, Motorola (United States)
Matt Monroe, Motorola (United States)
Carroll Casteel, Motorola (United States)
Mark Zaleski, Motorola (United States)

Published in SPIE Proceedings Vol. 4346:
Optical Microlithography XIV
Christopher J. Progler, Editor(s)

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