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Proceedings Paper

Advanced procedure to evaluate process performance at very low k1 based on device parameters linked to lithography and process data:II. Verification of cell layout based on integration of optical an
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Paper Abstract

This is an extension of our previous work where we discussed basic assumptions of device oriented process verification. Here, we propose an integrated procedure to verify the design of active devices and interconnections. It entails extraction of device, contact, and interconnect electrical performance based on optical simulation of layout geometries, including proximity correction features, combined with critical dimension (CD) variation and misalignment. A critical analysis, proposed in this work, made it possible to focus the simulation on the selected process corner options. We integrated multi-level optical and device simulation to verify dense layouts for deep sub- wavelength design rules in a six-transistor advanced memory cell.

Paper Details

Date Published: 14 September 2001
PDF: 8 pages
Proc. SPIE 4346, Optical Microlithography XIV, (14 September 2001); doi: 10.1117/12.435693
Show Author Affiliations
Artur P. Balasinski, Cypress Semiconductor (United States)
Walter Iandolo, Cypress Semiconductor (United States)
Devendra Joshi, Numerical Technologies, Inc. (United States)
Linard Karklin, Numerical Technologies, Inc. (United States)
Valery Axelrad, Sequoia Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 4346:
Optical Microlithography XIV
Christopher J. Progler, Editor(s)

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