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Proceedings Paper

Real-time debugger with bitstream configurator and C language design control for FPGAs
Author(s): Steve Casselman; John Schewel; Frank Wartel
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Paper Abstract

At the boundary between hardware and software, where FPGAs with 2,000,000 gates is just the beginning, we've found that the tools you have in your toolbox make all the difference. With larger and more feature rich programmable devices such as the VirtexTM Platform FPGA, even minors changes in the design can require hours of compile time. The combination of design complexity and component size is taxing current design entry and implementation tools, making the design cycle loner. The simulation-verification cycle doesn't mean the design will work in the final product. The engineer needs more than ever, to debug designs within the target hardware in real-time. We have built a series of integrated tools aimed at enhancing productivity at the last stages of product design, the final ten percent of the design that takes ninety percent of the time. The tools shown are not meant to replace current tools. These are advanced tools for the FPGA power user. Our goal is creating a set of tools specifically designed to provide better design control, dramatically reduce iteration times and enable real-time In-Circuit debugged in hardware. We have organized this series of tools as The Technology StackTM.

Paper Details

Date Published: 24 July 2001
PDF: 7 pages
Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434386
Show Author Affiliations
Steve Casselman, Virtual Computer Corp. (United States)
John Schewel, Virtual Computer Corp. (United States)
Frank Wartel, Virtual Computer Corp. (United States)

Published in SPIE Proceedings Vol. 4525:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry, Editor(s)

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