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Proceedings Paper

Model-based performance analysis for reconfigurable coprocessors
Author(s): Stephen M. Charlwood; Jon P. Mangnall; Steven F. Quigley
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Paper Abstract

Uni-processor and shared memory UMA multi-processor workstations are currently ubiquitous. The capabilities of such machines are commonly extended through the use of one or more application-specific coprocessors, located on the system expansion/peripheral bus, or a dedicated local bus. It is therefore considered worthwhile to investigate the limits of applicability of FPGA-based reconfigurable coprocessors when used to enhance such machines. In order to do this, it must be possible to estimate performance for coprocessor architectures that do not currently exist. This paper describes a method for generating estimates of performance for applications which make use of such reconfigurable coprocessors. By combining direct measurements on the target platform with model-based estimates and simulation data, estimates of performance can be synthesised which are accurate to better than +/- 5%.

Paper Details

Date Published: 24 July 2001
PDF: 12 pages
Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434383
Show Author Affiliations
Stephen M. Charlwood, Univ. of Birmingham (United Kingdom)
Jon P. Mangnall, Univ. of Birmingham (United Kingdom)
Steven F. Quigley, Univ. of Birmingham (United Kingdom)


Published in SPIE Proceedings Vol. 4525:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry, Editor(s)

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