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Proceedings Paper

Temporal partitioning of circuits for advanced partially reconfigurable systems
Author(s): Rajanikant Mohan; Aravind R. Dasu; Sethuraman Panchanathan
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Paper Abstract

Reconfigurable architectures are proving to be very effective in applications that involve the implementation of multiple compute-intensive algorithms, which share the same computing modules. With the advent of dynamically reconfigurable architectures, many temporal partitioning algorithms (TPA) have been proposed address the issue of area and time constraints. The main objective of TPA is to divide a large design into smaller sub-components so that they can be implemented over multiple reconfigurations. In this paper, we propose a new temporal partitioning process (TPP), which includes a modified TPA along with a port reallocation algorithm (PRA) to reduce the reconfiguration time to facilitate real-time implementation. The reduction in reconfiguration time is achieved by employing the knowledge of the function implemented in each logic block thereby effectively reusing the cells in the array in a selective manner. This avoids the need for complete reconfiguration and reduces the net reconfiguration time. The proposed approach has been tested on random graphs and on the MCNC benchmark circuits. Significant reduction in reconfiguration time has been achieved.

Paper Details

Date Published: 24 July 2001
PDF: 9 pages
Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434382
Show Author Affiliations
Rajanikant Mohan, Arizona State Univ. (United States)
Aravind R. Dasu, Arizona State Univ. (United States)
Sethuraman Panchanathan, Arizona State Univ. (United States)


Published in SPIE Proceedings Vol. 4525:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry, Editor(s)

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