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Proceedings Paper

Variable length decoder on dynamically reconfigurable cell array processor
Author(s): Kiyotaka Komoku; Takayuki Morishita; Fumihiro Hatano; Iwao Teramoto
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Paper Abstract

Three kinds of basic Variable Length Decoder were implemented on Dynamically Reconfigurable Cell Array Processor. Traditional method, Leading zeros method, Generated unique address method were discussed. The number of required resources for each Decoder was described. Especially, in Generated unique address method, the Variable Length Decoder circuit size on Dynamically Reconfigurable Cell Array Processor was quite small.

Paper Details

Date Published: 24 July 2001
PDF: 8 pages
Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434377
Show Author Affiliations
Kiyotaka Komoku, Okayama Prefectural Univ. (Japan)
Takayuki Morishita, Okayama Prefectural Univ. (Japan)
Fumihiro Hatano, Okayama Prefectural Univ. (Japan)
Iwao Teramoto, Okayama Prefectural Univ. (Japan)


Published in SPIE Proceedings Vol. 4525:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry, Editor(s)

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