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Proceedings Paper

Reconfigurable processors for handhelds and wearables: application analysis
Author(s): Rolf Enzler; Marco Platzner; Christian Plessl; Lothar Thiele; Gerhard Troester
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Paper Abstract

In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.

Paper Details

Date Published: 24 July 2001
PDF: 12 pages
Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434376
Show Author Affiliations
Rolf Enzler, Swiss Federal Institute of Technology/Zurich (Switzerland)
Marco Platzner, Swiss Federal Institute of Technology/Zurich (Switzerland)
Christian Plessl, Swiss Federal Institute of Technology/Zurich (Switzerland)
Lothar Thiele, Swiss Federal Institute of Technology/Zurich (Switzerland)
Gerhard Troester, Swiss Federal Institute of Technology/Zurich (Switzerland)


Published in SPIE Proceedings Vol. 4525:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry, Editor(s)

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