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Proceedings Paper

Network processor architecture for flexible buffer management in very high speed line interfaces
Author(s): Shimonishi Hideyuki; Murase Tutomu
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Paper Abstract

In this paper, the proposed architecture is described and the results obtained when evaluating it in a typical application program for traffic handling are reported. It is shown that the architecture enables Weighted Round Robin packet scheduling at 4.1 Gbps line speed, in addition to 10 Gbps IP packet forwarding and 2.4 Gbps IP/ATM multi-layer switching.

Paper Details

Date Published: 24 July 2001
PDF: 10 pages
Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434375
Show Author Affiliations
Shimonishi Hideyuki, NEC Corp. (Japan)
Murase Tutomu, NEC Corp. (Japan)


Published in SPIE Proceedings Vol. 4525:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry, Editor(s)

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