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Proceedings Paper

Run-time reconfigurable 2D discrete wavelet transform using JBits
Author(s): Jonathan Ballagh; Peter M. Athanas; Eric R. Keller
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Paper Abstract

With the growth in high performance multimedia applications, specialized hardware for certain tasks is desirable. While ASICs provide a solution addressing performance, they are unable to provide an optimal solution for a given problem instance. FPGAs can be used with run-time reconfiguration to dynamically customize a circuit. Optimizations leading to faster circuits and reduced logic can result. The paper discusses the implementation of a run-time parameterizable 2D Discrete Wavelet Transform core using the JBits tool suite. The motivation for such a core is discussed, as well the benefits afforded by dynamic circuit specialization.

Paper Details

Date Published: 24 July 2001
PDF: 9 pages
Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434374
Show Author Affiliations
Jonathan Ballagh, Virginia Polytechnic Institute and State Univ. (United States)
Peter M. Athanas, Virginia Polytechnic Institute and State Univ. (United States)
Eric R. Keller, Xilinx, Inc. (United States)


Published in SPIE Proceedings Vol. 4525:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry, Editor(s)

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