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Proceedings Paper

Highly reconfigurable communication protocol multiplexing element for SCOPH
Author(s): Gordon Brebner
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Paper Abstract

The Soft Circuitry Optimised Protocol Harness (SCOPH) project is concerned with implementing streaming data paths that perform communication protocol functions. The data paths are implemented dynamically using soft circuitry on a programmed logic array, based upon a small set of parameterised function blocks that are instantiated and linked together on a per-connection basis, and may also be modified during connections. This allows the use of optimised bespoke protocols, with handling of protocol functions at hardware speeds. This paper focuses on one particular pair of function blocks, for the demultiplexing and multiplexing of multiple connections sharing a single communication channel. An example would be multiple TCP port connections simultaneously active over a single IP channel. In the SCOPH context, a single data stream emanating from a main processor or from a network interface would be split into multiple data streams, which undergo protocol processing, and are then recombined into a single stream to a network interface or main processor respectively. The demultiplexor block always requires a means of selecting one of a number of streams, given addressing information in the data stream itself. Symmetrically, the multiplexor block must insert appropriate addressing information into the data stream. However, the main thrust of the paper is in comparing area-time trade-offs between using blocks with a (small) fixed number of streams always configured and using blocks that vary in size and shape with the current number of active streams. Both options are being investigated on a Xilinx Virtex FPGA, using JBits for the dynamic configuration.

Paper Details

Date Published: 24 July 2001
PDF: 8 pages
Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434372
Show Author Affiliations
Gordon Brebner, Univ. of Edinburgh (United Kingdom)

Published in SPIE Proceedings Vol. 4525:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry, Editor(s)

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