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Proceedings Paper

Reconfiguring an FPGA-based RISC for LNS arithmetic
Author(s): Mark G. Arnold; Mark D. Winkel
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Paper Abstract

Field Programmable Gate Arrays (FPGAs) have some difficulty with the implementation of floating-point operations. In particular, devoting the large number of slices needed by floating-point multipliers prohibits incorporating floating point into smaller, less expensive FPGAs. An alternative is the Logarithmic Number System (LNS), where multiplication and division are easy and fast. LNS also has the advantage of lower power consumption than fixed point. The problem with LNS has been the implementation of addition. There are many price/performance tradeoffs in the LNS design space between pure software and specialised-high-speed hardware. This paper focuses on a compromise between these extremes. We report on a small RISC core of our own design (loosely inspired by the popular ARM processor) in which only 4 percent additional investment in FPGA resources beyond that required for the integer RISC core more than doubles the speed of LNS addition compared to a pure software approach. Our approach shares resources in the datapath of the non-LNS parts of the RISC so that the only significant cost is the decoding and control for the LNS instruction. Since adoption of LNS depends on its cost effectiveness (e.g., FLOPs/slice), we compare our design against an earlier LNS ALU implemented in a similar FPGA. Our preliminary experiments suggest modest LNS-FPGA implementations, like ours, are more cost effective than pure software and can be as cost effective as more expensive LNS-FPGA implementations that attempt to maximise speed. Thus, our LNS-RISC fits in the Virtex-300, which is not possible for a comparable design.

Paper Details

Date Published: 24 July 2001
PDF: 11 pages
Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); doi: 10.1117/12.434371
Show Author Affiliations
Mark G. Arnold, Univ. of Manchester Institute of Science and Technology (United Kingdom)
Mark D. Winkel, XLNS Research (United States)

Published in SPIE Proceedings Vol. 4525:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III
John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry, Editor(s)

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