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Proceedings Paper

Optoelectronics silicon on insulator integrated circuits by porous silicon technology
Author(s): M. Balucani; G. Lamedica; V. Bondarenko; A. Ferrari
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Paper Abstract

This work reports on the CMOS-SOI devices based on porous silicon technology (PST) opening the possibility of wafer scale integration realizing on-chip optoelectronic integrated circuits by the PST. Silicon on insulator (SOI) structure based on the preferential anodization of n+ layer within n-/n+/n- were realized. Standard n-type Si (100) have been used as initial substrates. N+ layer have been formed by Sb ion implantation into the front and backside of the substrates followed by annealing. Then an epitaxial layer has been grown on the front of the wafers and projection photolithography using reactive ion etching of both the mask and the epitaxial layer has been used to define three dimensional pattern of islands wherein device components are formed. Characteristics and device layout are presented for partially depleted devices used to build ring oscillator showing that a 1.2 micron resolution in SOI porous silicon technology is comparable with a 0.5 micron CMOS technology.

Paper Details

Date Published: 29 June 2001
PDF: 7 pages
Proc. SPIE 4430, ROMOPTO 2000: Sixth Conference on Optics, (29 June 2001); doi: 10.1117/12.432919
Show Author Affiliations
M. Balucani, Univ. degli Studi di Roma La Sapienza (Italy)
G. Lamedica, Univ. degli Studi di Roma La Sapienza (Italy)
V. Bondarenko, Univ. degli Studi di Roma La Sapienza (Italy)
A. Ferrari, Univ. degli Studi di Roma La Sapienza (Italy)

Published in SPIE Proceedings Vol. 4430:
ROMOPTO 2000: Sixth Conference on Optics
Valentin I. Vlad, Editor(s)

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