Share Email Print
cover

Proceedings Paper

Realizing optimum yields on IC products fabricated in current and future process technologies
Author(s): Fred Lakhani
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Realizing optimum integrated circuit yield has always been a formidable challenge for the semiconductor device manufacturer. With continuing reduction in minimum feature size, ongoing introduction of new materials and device architectures and inclusion of diverse functional blocks in the chip design, this challenge will continue to grow with each successive process technology node. The key focus areas that must be optimized to meet this challenge include: design for manufacturing and design for test; process technology development and transfer; modeling of random and systematic defect limited yields; detection and characterization of yield detracting defects; and integrated yield management for rapid defect sourcing. This paper will provide an overview of the tools and methods used in the industry today and outline future needs for achieving optimum yields with special emphasis on the focus areas listed above.

Paper Details

Date Published: 5 June 2001
PDF: 10 pages
Proc. SPIE 4275, Metrology-based Control for Micro-Manufacturing, (5 June 2001); doi: 10.1117/12.429360
Show Author Affiliations
Fred Lakhani, International SEMATECH (United States)


Published in SPIE Proceedings Vol. 4275:
Metrology-based Control for Micro-Manufacturing
Kenneth W. Tobin; Fred Lakhani, Editor(s)

© SPIE. Terms of Use
Back to Top