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Proceedings Paper

Three-dimensional micro-optical architecture for chip-level optical interconnects
Author(s): Dennis W. Prather; Sriram Venkatraraman; Marion R. LeCompte; Harry E. Bates Jr.; Fouad E. Kiamilev
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Paper Abstract

As processor speeds enter the Gigahertz regime, the disparity between processing time and memory access time plays an increasingly important role in the overall limitation of processor performance. Furthermore, as the components continue to shrink in size, the limitations in interconnect density and bandwidth serve to exacerbate communication bottlenecks. To address these issues, we propose a 3D architecture based on through-wafer vertical optical interconnects. Our system is monolithically fabricated on a single host substrate and preserves the VLSI-scale of integration by using meso-scopic diffractive optical elements for beam fan-out and signal distribution at the chip level.

Paper Details

Date Published: 30 May 2001
PDF: 11 pages
Proc. SPIE 4292, Optoelectronic Interconnects VIII, (30 May 2001); doi: 10.1117/12.428031
Show Author Affiliations
Dennis W. Prather, Univ. of Delaware (United States)
Sriram Venkatraraman, Univ. of Delaware (United States)
Marion R. LeCompte, Univ. of Delaware (United States)
Harry E. Bates Jr., Univ. of Delaware (United States)
Fouad E. Kiamilev, Univ. of Delaware (United States)

Published in SPIE Proceedings Vol. 4292:
Optoelectronic Interconnects VIII
Suning Tang; Yao Li, Editor(s)

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