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Proceedings Paper

Planarization wrinkle in CIS color filter process
Author(s): Chih-Kung Chang; Yu-Kung Hsiao; Shang-Yung Yang; Kuo-Liang Lu
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Paper Abstract

The mechanism of planarization wrinkle defect in complementary metal oxide semiconductor (CMOS) color filter process is discussed in this paper. The wrinkle phenomena occurred as the planarization resist thickness decreased and became worse after high temperature baking was implemented. In experiment, the effect of factors on the wrinkle with KLA scanning such as resist thickness, soft bake temperature and time after resist coating and development puddle time were analyzed. From the data, the wrinkle is connectable with the developer penetration into and break through the resist film. Some solutions can be applied to solve this problem. Strengthening the resist film by increasing expose energy to get higher degree of polymerization is the best solution. Increasing resist thickness also can inhibit wrinkle but it is limited by the overall stack height for optimizing microlens focal length. Prolonging the soft bake time and reducing the puddle time of development to eliminate the penetration effect of developer are not obvious.

Paper Details

Date Published: 23 April 2001
PDF: 8 pages
Proc. SPIE 4406, In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II, (23 April 2001); doi: 10.1117/12.425282
Show Author Affiliations
Chih-Kung Chang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Yu-Kung Hsiao, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Shang-Yung Yang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Kuo-Liang Lu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)


Published in SPIE Proceedings Vol. 4406:
In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II
Gudrun Kissinger; Larg H. Weiland, Editor(s)

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