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Proceedings Paper

Large polysilicon grain defects in gate deposition due to prior contamination
Author(s): Kathleen Terryll; Miguel Angel Garcia; Pablo S. Dominguez
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Paper Abstract

In this article, we describe the experiments and analysis of a contamination caused defect, which only appears after the polysilicon gate deposition process of a CMOS semiconductor chip. The polysilicon defects are about 0.3 micrometer in diameter. The defects appear densely in one area of the wafer and they closely resemble the phosphorous contaminate defect, although no analysis method could detect the element(s). The most notable characteristic is the defect density, which varies with the different areas within a chip. There are several common conditions which are notable. First, the defect only occurs in 3V technology. Secondly, the defect occurs where the gate oxidation boat contacts the wafer. The most notable experiment was the rotation of the wafers in the gate oxidation, processing step. The wafers were rotated about 20 degrees before they were loaded into the boats and the poly bump defect area also moved about 20 degrees. Thirdly, the defect occurs sporadically with no relation to common process tools or maintenance. Recently, the gate oxidation process was changed from horizontal to vertical furnaces and since this change there has not been any poly bump defects event.

Paper Details

Date Published: 23 April 2001
PDF: 7 pages
Proc. SPIE 4406, In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II, (23 April 2001); doi: 10.1117/12.425275
Show Author Affiliations
Kathleen Terryll, Agere Systems (Spain)
Miguel Angel Garcia, Agere Systems (Spain)
Pablo S. Dominguez, Agere Systems (Spain)


Published in SPIE Proceedings Vol. 4406:
In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II
Gudrun Kissinger; Larg H. Weiland, Editor(s)

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