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Proceedings Paper

Localization of defects using checkerboard test structures
Author(s): Sven-Olaf Schellenberg
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Paper Abstract

Defects in semiconductor industry become more important by shrinking structures and increasing complexity of process. Therefore the size of a killer defect becomes smaller and it is not easy to find them with optical inspection tools. In addition Inspection tools are not able to say something about electrical effects from defects which are found. With Checkerboard Test Structures it is possible to locate electrical defects. In fact these special test structures will be tested at the end of the process, like an usual function test. A special developed algorithm allows low quantity of pads. This gives a high spatial resolution and on the other hand we have good ratio between active and passive area. A reduction of a statistical failure could be reached, because it is not necessary to calculate the defect density from a small region. In particular special defect distribution like cluster can be considered. With this structures different layers can be examined for disconnections and short-circuits. Therefore it is possible to locate defects in one layer or between two layers. So the defect density for the sensitive dielectrica between two layers, like any kind of oxide can be calculated. The karree test structures can be used very good as an inline-defectmonitoring, because there is no difference from the original technology of proces. There are also no differences in time for processing and for testing, so Karreeteststructures is an optimal representation for your process.

Paper Details

Date Published: 23 April 2001
PDF: 5 pages
Proc. SPIE 4406, In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II, (23 April 2001); doi: 10.1117/12.425270
Show Author Affiliations
Sven-Olaf Schellenberg, ELMOS Elektronik in MOS-Technologie GmbH (Germany)

Published in SPIE Proceedings Vol. 4406:
In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II
Gudrun Kissinger; Larg H. Weiland, Editor(s)

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