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Proceedings Paper

Process-induced threshold voltage fluctuations on SOI fully depleted technology
Author(s): Olivier Potavin; Abdelaziz Ahaitouf
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Paper Abstract

SOI devices have been shown to present better performances as compared to Bulk MOSFETs for low power-low voltage IC's. Thick film partially depleted SOI transistors have mainly been proposed up to now. However, for 0.1 and sub-0.1 micrometer devices or ultra low power devices, fully depleted thin and ultra-thin SOI MOSFETs with recess channel seem to be the best candidates. Indeed, those devices have been shown to present interesting properties in term of short channel effects, subthreshold swing and electron temperature. But one of the major bottleneck of SOI devices is the final film thickness control. According to the Lim and Fossum long channel model, the front interface threshold voltage is linearly dependent with the doping and the final silicon film thickness. Cumulative fluctuations of oxide growths and the non self alignment of the gate induce a strong threshold voltage variation on wafer and on a whole run. According to experimental results and 2D simulations the impact of the film thickness fluctuations and gate misalignment on the electrical performance will be presented. The maximum variations allowed to reach the design specifications will be extracted and finally a process windows will be defined.

Paper Details

Date Published: 23 April 2001
PDF: 9 pages
Proc. SPIE 4406, In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II, (23 April 2001); doi: 10.1117/12.425262
Show Author Affiliations
Olivier Potavin, EM Microelectronic-Marin SA (Switzerland)
Abdelaziz Ahaitouf, Ecole Polytechnique Federale de Lausanne (Switzerland)


Published in SPIE Proceedings Vol. 4406:
In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II
Gudrun Kissinger; Larg H. Weiland, Editor(s)

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