Share Email Print
cover

Proceedings Paper

Front-end-of-line process development using 193-nm lithography
Author(s): Ivan K.A. Pollentier; Monique Ercken; Astrid Eliat; Christie Delvaux; Patrick Jaenen; Kurt G. Ronse
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

It is expected that 193nm lithography will be introduced in front-end-of-line processing for all critical layers at the 100nm node, and possibly also for some layers at the 130nm node, where critical layers are required to have the lowest mask cost. These processes are currently being investigated at IMEC for CMOS logic applications. While the lithographic performance of 193 nm resists has improved significantly in the last year, most materials still have important processing issues that need further improvement. On one hand, the resists material itself suffers from for example poor dry etch resistance and SEM CD shrinkage. On the other hand, interaction with other materials such as SiON inorganic ARCs becomes more challenging in terms of footing behavior, adhesion, and line edge roughness. In this paper, the 193nm processing experience gained at IMEC will be outlined, as well as solutions for manufacturability. Front- end-of-line integration results will also be shown, mainly for gate applications. It will be demonstrated that currently several commercial resist are capable of printing 130nm gates within the +/- 10 percent CD tolerance, even after gate etch. The impact of line edge roughness will also be discussed. Finally, the feasibility of printing 100nm logic patterns using only binary masks has been demonstrated, including gate etch.

Paper Details

Date Published: 26 April 2001
PDF: 12 pages
Proc. SPIE 4404, Lithography for Semiconductor Manufacturing II, (26 April 2001); doi: 10.1117/12.425235
Show Author Affiliations
Ivan K.A. Pollentier, IMEC (Belgium)
Monique Ercken, IMEC (Belgium)
Astrid Eliat, IMEC (Belgium)
Christie Delvaux, IMEC (Belgium)
Patrick Jaenen, IMEC (Belgium)
Kurt G. Ronse, IMEC (Belgium)


Published in SPIE Proceedings Vol. 4404:
Lithography for Semiconductor Manufacturing II
Chris A. Mack; Tom Stevenson, Editor(s)

© SPIE. Terms of Use
Back to Top