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Proceedings Paper

Overlay improvement on 0.15-um production with ASML IOSc (improved overlay scanner) package
Author(s): Kun-Yi Liu; S. S. Wang; Y. Y. Chu; J. C. Hsieh
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Paper Abstract

The alignment accuracy has become a big challenge in sub- micro technology, especially below 0.15um technology. Scanner induced alignment error like RICO effect or WICO effect are big problems for foundry fab overlay control. For improving scanner overlay performance, ASML has provided an overlay improving package, IOSc to solve these issues. IOSc package includes four major parts of hardware improvement. (1) Phase 3 reticle chuck proposes to improve image distortion and overlay. (2) Phase modulators for TTL and Athena propose to reduce RICO effect and WICO effect. (3) Continuous clamping wafer table proposes to minimize wafer distortion. (4) Wafer stage air shower proposes to improve the stage travel stability.

Paper Details

Date Published: 26 April 2001
PDF: 11 pages
Proc. SPIE 4404, Lithography for Semiconductor Manufacturing II, (26 April 2001); doi: 10.1117/12.425234
Show Author Affiliations
Kun-Yi Liu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
S. S. Wang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Y. Y. Chu, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
J. C. Hsieh, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)


Published in SPIE Proceedings Vol. 4404:
Lithography for Semiconductor Manufacturing II
Chris A. Mack; Tom Stevenson, Editor(s)

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