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Proceedings Paper

ArF lithography: challenges, resolution capability, and the mask error enhancement function (MEEF)
Author(s): Marina V. Plat; Christopher F. Lyons; Amada Wilkison; Jeff A. Schefske; Hung-Eil Kim
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Paper Abstract

Early insertion of ArF nm lithography will occur at the 130 nm node in 2001. Process development for the 100nm node will also occur this year. Both aggressive gate length reductions and minimum pitch design rules below 250nm present immediate challenges for the new ArF technology. Gate line widths will approach one half of the wavelength of the exposure system.

Paper Details

Date Published: 26 April 2001
PDF: 8 pages
Proc. SPIE 4404, Lithography for Semiconductor Manufacturing II, (26 April 2001); doi: 10.1117/12.425202
Show Author Affiliations
Marina V. Plat, Advanced Micro Devices, Inc. (United States)
Christopher F. Lyons, Advanced Micro Devices, Inc. (United States)
Amada Wilkison, Advanced Micro Devices, Inc. (United States)
Jeff A. Schefske, Advanced Micro Devices, Inc. (United States)
Hung-Eil Kim, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 4404:
Lithography for Semiconductor Manufacturing II
Chris A. Mack; Tom Stevenson, Editor(s)

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