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Proceedings Paper

Architecture for hardware compression/decompression of large images
Author(s): Mohamed Akil; Laurent Perroton; Stephane Gailhard; Julien Denoulet; Frederic Bartier
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Paper Abstract

In this article, we present a popular loseless compression/decompression algorithm, GZIP, and the study to implement it on a FPGA based architecture. The algorithm is loseless, and applied to 'bi-level' images of large size. It insures a minimum compression rate for the images we are considering. The proposed architecture for the compressor is based ona hash table and the decompressor is based on a parallel decoder of the Huffman codes.

Paper Details

Date Published: 27 April 2001
PDF: 8 pages
Proc. SPIE 4303, Real-Time Imaging V, (27 April 2001); doi: 10.1117/12.424956
Show Author Affiliations
Mohamed Akil, Ecole Superieure d'Ingenieurs en Electrotechnique et Electronique (France)
Laurent Perroton, Ecole Superieure d'Ingenieurs en Electrotechnique et Electronique (France)
Stephane Gailhard, Ecole Superieure d'Ingenieurs en Electrotechnique et Electronique (France)
Julien Denoulet, Ecole Superieure d'Ingenieurs en Electrotechnique et Electronique (France)
Frederic Bartier, Oce-industries France (France)


Published in SPIE Proceedings Vol. 4303:
Real-Time Imaging V
Nasser Kehtarnavaz, Editor(s)

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