Share Email Print

Proceedings Paper

Processor architecture of MBAP for embedded image understanding system
Author(s): Peng Liu; Qingdong Yao; Song Wu; Qiaohai Pan; JinMei Lai
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Processor's architecture has great effect on the performance of whole processor array. In order to improve the performance of SIMD array architecture, we modified the structure of BAP (bit-serial array processor) processing element based on the BAP128 processor. The array processor chip of modified bit-serial array processor (MBAP in abbreviation) with 0.35 micrometers CMOS technology is designed for embedded image understanding system. This paper not only presents MBAP architecture, but also gives the architecture feature about this design. Toward basic macro instructions and low-level processing algorithms of image understanding, the performance of BAP and MBAP is compared. The result shows that the performance of MBAP has much improvement on BAP, at the cost of increasing 5% chip resource.

Paper Details

Date Published: 29 March 2001
PDF: 8 pages
Proc. SPIE 4313, Media Processors 2001, (29 March 2001); doi: 10.1117/12.420797
Show Author Affiliations
Peng Liu, Zhejiang Univ. (China)
Qingdong Yao, Zhejiang Univ. (China)
Song Wu, Zhejiang Univ. (China)
Qiaohai Pan, Zhejiang Univ. (China)
JinMei Lai, Zhejiang Univ. (China)

Published in SPIE Proceedings Vol. 4313:
Media Processors 2001
Sethuraman Panchanathan; V. Michael Bove; Subramania I. Sudharsanan, Editor(s)

© SPIE. Terms of Use
Back to Top