Share Email Print
cover

Proceedings Paper

Trends in merged DRAM-logic computing
Author(s): Joseph Gebis
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Recent trends suggest that the current practice of fabricating DRAM and logic on separate dies and different processes should be reexamined. The gap between processing speed and memory latency is growing at 50% per year, and portable systems, where physical size and weight are critical issues, are becoming more popular. Merged DRAM-logic processes address these issues by combining DRAM and logic on a single die; this technology also promises to offer advantages such as increased memory bandwidth, reduced power consumption, and greater flexibility in memory organization. Merged DRAM-logic chips have already been successfully used in several commercial products. More commercial products are planned, and academic research projects are examining future uses of merged DRAM- logic processing. This paper describes the current state of merged DRAM-logic chips and examines proposed architectures, their performance and applications. Finally, tradeoffs and challenges related to the technology are discussed.

Paper Details

Date Published: 17 November 2000
PDF: 8 pages
Proc. SPIE 4109, Critical Technologies for the Future of Computing, (17 November 2000); doi: 10.1117/12.409220
Show Author Affiliations
Joseph Gebis, Univ. of California/Berkeley (United States)


Published in SPIE Proceedings Vol. 4109:
Critical Technologies for the Future of Computing
Sunny Bains; Leo J. Irakliotis, Editor(s)

© SPIE. Terms of Use
Back to Top