Share Email Print

Proceedings Paper

Giga-cache: a high performance optoelectronic memory architecture
Author(s): Paul Lukowicz
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

High memory latency is among the most critical performance factors in today's computers. To a degree it can be attributed to the high cost of fast (but low density) SRAM memory compared to slow (but high density) DRAM components. However the most important factor is the increase in access time in large memory systems caused by the communication latency. The paper describes how optical interconnections with a simple, regular topology and a modest number of optical IOs could be used to implement a memory system with a capacity of up to 1 GByte and a latency on the order of magnitude of a second level cache. The system relies on the direct integration of optical IOs on top of VLSI circuits which allows the processor to have direct, low latency, high bandwidth interconnection with hundreds of components.

Paper Details

Date Published: 17 November 2000
PDF: 9 pages
Proc. SPIE 4109, Critical Technologies for the Future of Computing, (17 November 2000); doi: 10.1117/12.409219
Show Author Affiliations
Paul Lukowicz, Swiss Federal Institute of Technology/Zurich (Switzerland)

Published in SPIE Proceedings Vol. 4109:
Critical Technologies for the Future of Computing
Sunny Bains; Leo J. Irakliotis, Editor(s)

© SPIE. Terms of Use
Back to Top