Share Email Print
cover

Proceedings Paper

20-GFLOPS QR processor on a Xilinx Virtex-E FPGA
Author(s): Richard L. Walke; Robert W. M. Smith; Gaye Lightbody
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In high-sample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable Gate Array (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimized to the target application to minimize component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterized implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

Paper Details

Date Published: 13 November 2000
PDF: 11 pages
Proc. SPIE 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X, (13 November 2000); doi: 10.1117/12.406508
Show Author Affiliations
Richard L. Walke, Defence Evaluation and Research Agency Malvern (United Kingdom)
Robert W. M. Smith, Defence Evaluation and Research Agency Malvern (United Kingdom)
Gaye Lightbody, Queen's Univ. of Belfast (United Kingdom)


Published in SPIE Proceedings Vol. 4116:
Advanced Signal Processing Algorithms, Architectures, and Implementations X
Franklin T. Luk, Editor(s)

© SPIE. Terms of Use
Back to Top