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Proceedings Paper

High-performance fine-grained pipelined LMS algorithm in Virtex FPGA
Author(s): Lok-Kee Ting; Roger F. Woods; Colin F. N. Cowan; P. R. Cork; C. L.J. Sprigings
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Paper Abstract

This paper presents the design, implementation, and verification of fine-grained pipelined Least-Mean-Square (LMS) adaptive Finite- Impulse-Response (FIR) filters in Virtex FPGA technology. The paper focuses on the impact of introducing pipelining into the LMS filter. While pipelining provides a speed increase, the additional effect is to introduce delay into the error feedback loop which degrades performance. This effect is overcome through the use of look-ahead and delayed LMS based algorithms. In addition, the paper shows that FPGA technology, such as the Virtex FPGA is an ideal platform for this implementation, as the costs of pipelining are offset by the availability of high levels of flip flops within the FPGA architecture. A pipelined momentum LMS algorithm is identified, which is considered to offer a better convergence behavior and tracking capability than the pipelined LMS algorithm. Detailed performance results including area and timing figures based on actual FPGA layout are given.

Paper Details

Date Published: 13 November 2000
PDF: 12 pages
Proc. SPIE 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X, (13 November 2000); doi: 10.1117/12.406507
Show Author Affiliations
Lok-Kee Ting, Queen's Univ. of Belfast (United Kingdom)
Roger F. Woods, Queen's Univ. of Belfast (United Kingdom)
Colin F. N. Cowan, Queen's Univ. of Belfast (United Kingdom)
P. R. Cork, Defence Evaluation and Research Agency Malvern (United Kingdom)
C. L.J. Sprigings, Defence Evaluation and Research Agency Malvern (United Kingdom)


Published in SPIE Proceedings Vol. 4116:
Advanced Signal Processing Algorithms, Architectures, and Implementations X
Franklin T. Luk, Editor(s)

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