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Proceedings Paper

Fast multiply-accumulate architecture
Author(s): Robert T. Grisamore; Earl E. Swartzlander
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Paper Abstract

A high speed multiplier-accumulator (MAC) architecture is presented that accepts up to 2k pairs of n-bit 2's complement input operands and generates one 2n+k-bit result. The implementation uses a 2 stage pipelined multiplier with Dadda reduction and a single carry propagating adder. A significant speedup is achieved with this implementation over conventional MAC designs. The complexity is reduced slightly. An example design is presented with 24-bit input operands designed using a 0.35 micrometer CMOS technology.

Paper Details

Date Published: 13 November 2000
PDF: 9 pages
Proc. SPIE 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X, (13 November 2000); doi: 10.1117/12.406506
Show Author Affiliations
Robert T. Grisamore, SigmaTel Inc. (United States)
Earl E. Swartzlander, Univ. of Texas at Austin (United States)


Published in SPIE Proceedings Vol. 4116:
Advanced Signal Processing Algorithms, Architectures, and Implementations X
Franklin T. Luk, Editor(s)

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