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Proceedings Paper

Low-cost speech recognition system for small vocabulary and independent speaker
Author(s): Chih Chiang Teh; Ching Chuen Jong; Liter Siek
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Paper Abstract

In this paper an ASIC implementation of a low cost speech recognition system for small vocabulary, 15 isolated word, speaker independent is presented. The IC is a digital block that receives a 12 bit sample with a sampling rate of 11.025 kHz as its input. The IC is running at 10 MHz system clock and targeted at 0.35 micrometers CMOS process. The whole chip, which includes the speech recognition system core, RAM and ROM contains about 61000 gates. The die size is 1.5 mm by 3 mm. The current design had been coded in VHDL for hardware implementation and its functionality is identical with the Matlab simulation. The average speech recognition rate for this IC is 89 percent for 15 isolated words.

Paper Details

Date Published: 24 October 2000
PDF: 4 pages
Proc. SPIE 4228, Design, Modeling, and Simulation in Microelectronics, (24 October 2000); doi: 10.1117/12.405414
Show Author Affiliations
Chih Chiang Teh, Nanyang Technological Univ. (Singapore)
Ching Chuen Jong, Nanyang Technological Univ. (Singapore)
Liter Siek, Nanyang Technological Univ. (Singapore)


Published in SPIE Proceedings Vol. 4228:
Design, Modeling, and Simulation in Microelectronics
Bernard Courtois; Serge N. Demidenko; Lee Y. Lau, Editor(s)

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