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Proceedings Paper

Delay-bound determination for path constraint satisfaction
Author(s): Nadine Azemard; Michel Aline; Daniel Auvergne
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Paper Abstract

This paper addresses the problem of path constraint satisfaction form delay bound determination. Based on a path delay profiling tool a method is developed to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with transistor sizing conditions, upper and lower bounds of delay are defined and characterized in terms of loading factors. Using these bounds as a reference, a method is developed to define average loading factors and equivalently transistor size allowing to satisfy timing constraint on critical path. Examples of application are given on different ISCAS circuits.

Paper Details

Date Published: 24 October 2000
PDF: 8 pages
Proc. SPIE 4228, Design, Modeling, and Simulation in Microelectronics, (24 October 2000); doi: 10.1117/12.405403
Show Author Affiliations
Nadine Azemard, Univ. Montpellier II (France)
Michel Aline, Univ. Montpellier II (France)
Daniel Auvergne, Univ. Montpellier II (France)

Published in SPIE Proceedings Vol. 4228:
Design, Modeling, and Simulation in Microelectronics
Bernard Courtois; Serge N. Demidenko; Lee Y. Lau, Editor(s)

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