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Proceedings Paper

Data path allocation for low power in high-level synthesis
Author(s): Yu Hong Zheng; Ching Chuen Jong; Hongwei Zhu
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Paper Abstract

This paper presents an approach for data path allocation in high-level synthesis aiming at power reduction. In this approach, the register allocation and module allocation are performed in the same phase in polynomial time. The power consumption is reduced by minimizing the functional switching and switched capacitance of the implementation architecture. The experimental results confirm the viability and usefulness of the approach in minimizing power consumption while keeping the number of registers and interconnections to the optimal.

Paper Details

Date Published: 24 October 2000
PDF: 6 pages
Proc. SPIE 4228, Design, Modeling, and Simulation in Microelectronics, (24 October 2000); doi: 10.1117/12.405402
Show Author Affiliations
Yu Hong Zheng, STMicroelectronics Asia Pacific Pte. Ltd. (Singapore)
Ching Chuen Jong, Nanyang Technological Univ. (Singapore)
Hongwei Zhu, Nanyang Technological Univ. (Singapore)


Published in SPIE Proceedings Vol. 4228:
Design, Modeling, and Simulation in Microelectronics
Bernard Courtois; Serge N. Demidenko; Lee Y. Lau, Editor(s)

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