Share Email Print

Proceedings Paper

Interconnection optimization during high-level synthesis of digital systems
Author(s): Hongwei Zhu; Ching Chuen Jong; Yu Hong Zheng
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

With increasing design complexity of digital systems and small device features in sub-micron technologies, interconnection in the digital systems becomes more significant. In this paper, a technique for data path allocation aiming at interconnection optimization is presented. Not only can it optimize the interconnections of the design, but also it enables designers to balance the register cost and interconnection cost. Experimental test results show that this technique can produce good designs.

Paper Details

Date Published: 24 October 2000
PDF: 7 pages
Proc. SPIE 4228, Design, Modeling, and Simulation in Microelectronics, (24 October 2000); doi: 10.1117/12.405401
Show Author Affiliations
Hongwei Zhu, Nanyang Technological Univ. (Singapore)
Ching Chuen Jong, Nanyang Technological Univ. (Singapore)
Yu Hong Zheng, STMicroelectronics Asia Pacific Pte. Ltd. (Singapore)

Published in SPIE Proceedings Vol. 4228:
Design, Modeling, and Simulation in Microelectronics
Bernard Courtois; Serge N. Demidenko; Lee Y. Lau, Editor(s)

© SPIE. Terms of Use
Back to Top