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Proceedings Paper

Novel algorithm for hot-carrier lifetime projection on thick gate PMOSFETs fabricated by 0.18-um CMOS technology
Author(s): Bin Bin Jie; Indrajit Manna; Xu Zeng; Qiang Guo; Keng Foo Lo
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Paper Abstract

It is critical how to project hot-carrier lifetime form wafer level hot-carrier injection (HCl) test data, due to the limited stress time. It is well known that both oxide charge formation and interface trap generation affect the degradation of thick gate PMOSFETs fabricated by 0.18 micrometers technology. Based on it, a new fitting mode and the corresponding fitting algorithm were proposed. Form only one experimental curve of any degradation versus stress time under any HCl stress condition, the corresponding fitting curve can be obtained using this model. Form the fitting curve, the hot-carrier lifetime under the corresponding stress condition can be extracted. It is shown here that the model is quite accurate. This algorithm is quite robust to extract HCl lifetime as well.

Paper Details

Date Published: 23 October 2000
PDF: 7 pages
Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); doi: 10.1117/12.404884
Show Author Affiliations
Bin Bin Jie, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Indrajit Manna, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Xu Zeng, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Qiang Guo, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Keng Foo Lo, Chartered Semiconductor Manufacturing, Ltd. (Singapore)

Published in SPIE Proceedings Vol. 4229:
Microelectronic Yield, Reliability, and Advanced Packaging
Cher Ming Tan; Yeng-Kaung Peng; Mali Mahalingam; Krishnamachar Prasad, Editor(s)

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