Share Email Print
cover

Proceedings Paper

System-level I/O power modeling
Author(s): William P. Pinello; P. R. Patel; Yuang-Liang Li
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

A methodology is proposed for the electrical characterization of electronic packages in a system-level environment. Modeling and simulation results show the capability of the method by demonstrating both power delivery and I/O signal integrity analysis in a unified environment. In addition to flexibility, the proposed method is capable of achieving accurate results in a fraction of the time as was previously required.

Paper Details

Date Published: 23 October 2000
PDF: 4 pages
Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); doi: 10.1117/12.404882
Show Author Affiliations
William P. Pinello, Intel Corp. (United States)
P. R. Patel, Intel Corp. (United States)
Yuang-Liang Li, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 4229:
Microelectronic Yield, Reliability, and Advanced Packaging
Cher Ming Tan; Yeng-Kaung Peng; Mali Mahalingam; Krishnamachar Prasad, Editor(s)

© SPIE. Terms of Use
Back to Top