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Proceedings Paper

Comprehensive methodology for integrated circuit in-line defect classification
Author(s): Richard L. Guldi; Douglas E. Paradis; Nagarajan Sridhar; Jesse B. Hightower
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Paper Abstract

The earliest attempts by human inspectors to classify defects found during in-line inspection of integrated circuits were fraught with difficulties in clarifying defect definitions and in training a diverse and changing inspector staff. These deficiencies were exacerbated by the challenges of expanding classification categories as new defects were discovered. Our diversified product mix had accumulated a knowledge base of approximately seventy defect types, posing a formidable learning challenge for even the most knowledgeable inspector. Not surprisingly, the average accuracy of the group in classifying defects was approximately 55 percent, and even the best inspector scored around 70 percent. To address these issues, we developed a comprehensive methodology for classifying defects. This methodology includes both word descriptions of the physical appearance of defects and a hierarchical questionnaire leading to precise defect classification. After adopting this methodology and implementing strong training programs, our team significantly improved its defect review process, ultimately reaching approximately 80 percent classification accuracy. With this degree of accuracy, we were able to implement defect specific statistical process control charts, together with formalized 'decision tree' procedures for correcting defect excursions. These formalisms then became an effective part of the fab's yield improvement program. Today, as technology advances into the realm of automatic defect classification (ADC), the lessons learned from human defect inspection form a strong foundation by establishing a comprehensive set of defect categories uniquely related to causality and supporting defect identification standards that can be used by the entire community of ADC training engineers.

Paper Details

Date Published: 23 October 2000
PDF: 7 pages
Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); doi: 10.1117/12.404860
Show Author Affiliations
Richard L. Guldi, Texas Instruments Inc. (United States)
Douglas E. Paradis, Texas Instruments Inc. (United States)
Nagarajan Sridhar, Texas Instruments Inc. (United States)
Jesse B. Hightower, Texas Instruments Inc. (United States)

Published in SPIE Proceedings Vol. 4229:
Microelectronic Yield, Reliability, and Advanced Packaging
Cher Ming Tan; Yeng-Kaung Peng; Mali Mahalingam; Krishnamachar Prasad, Editor(s)

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