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Proceedings Paper

Design and implementation of an FPGA-based processor for compressed images
Author(s): Venkataramanan S. Balakrishnan; Hardy Joseph Pottinger; Fikret Ercal; Mukesh Agarwal
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Paper Abstract

This paper deals with the implementation of a systolic array architecture in hardware using FPGAs for processing compressed binary images without decompressing them. Specifically, run-length encoding (RLE) is used for compression. Processing images in compressed form provides a significant speedup in the computation. Using a systolic architecture and implementing it in hardware further increases the speed.

Paper Details

Date Published: 9 October 2000
PDF: 11 pages
Proc. SPIE 4118, Parallel and Distributed Methods for Image Processing IV, (9 October 2000); doi: 10.1117/12.403594
Show Author Affiliations
Venkataramanan S. Balakrishnan, Univ. of Missouri/Rolla (United States)
Hardy Joseph Pottinger, Univ. of Missouri/Rolla (United States)
Fikret Ercal, Univ. of Missouri/Rolla (United States)
Mukesh Agarwal, Univ. of Missouri/Rolla (United States)


Published in SPIE Proceedings Vol. 4118:
Parallel and Distributed Methods for Image Processing IV
Hongchi Shi; Patrick C. Coffield; Divyendu Sinha, Editor(s)

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