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Proceedings Paper

FPGA-based parallel implementation for the lifting discrete wavelet transform
Author(s): Nazeeh Aranki; Wenqing Jiang; Antonio Ortega
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Paper Abstract

The rapidly increasing popularity of the discrete wavelet transform (DWT) as an effective tool in many signal processing and data compression applications, and its integration into JPEG 2000 has given rise to various DWT algorithms and their VLSI implementations to reduce complexity and enhance performance. In this paper, we present an efficient hardware implementation of the discrete wavelet transform and its deployment on a reconfigurable FPGA based platform. Our implementation is a novel architecture based on the lifting factorization of the wavelet filter banks. This factorization leads to a block based parallel DWT architecture suitable for hardware implementation. To overcome the communication overhead associated with the DWT block transform, we utilize the new Overlap-State1,2 technique to compute the DWT near block boundaries. A VHDL description of the lifting polyphase factorization architecture was developed and ported to an FPGA hardware platform that was chosen to allow partial and full reconfigurability to accommodate various applications with different filter banks. Our hardware implementation improves the performance by better than twofold speed up when compared to an efficient pipelined FPGA based implementation.

Paper Details

Date Published: 9 October 2000
PDF: 12 pages
Proc. SPIE 4118, Parallel and Distributed Methods for Image Processing IV, (9 October 2000); doi: 10.1117/12.403593
Show Author Affiliations
Nazeeh Aranki, Jet Propulsion Lab. (United States)
Wenqing Jiang, Univ. of Southern California (United States)
Antonio Ortega, Univ. of Southern California (United States)

Published in SPIE Proceedings Vol. 4118:
Parallel and Distributed Methods for Image Processing IV
Hongchi Shi; Patrick C. Coffield; Divyendu Sinha, Editor(s)

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