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Proceedings Paper

Fast scheduling and placement methods for C to hardware/software compilation
Author(s): Kia Bazargan; Majid Sarrafzadeh
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Paper Abstract

Advances in the FPGA technology, both in terms of device capacity and architecture, have resulted in introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. To keep up with the ever-growing performance expectations of such systems, designers need new methodologies and tools for developing reconfigurable computing systems (RCS). This paper addresses the need for fast compilation and physical design phase to be used in application development/debugging/testing cycle for RCS. We present a high-level synthesis approach that is integrated with placement, hence making the compilation cycle much faster. On the average, our tool generates the VHDL code (and the corresponding placment information) from the data flow graph of a program in less than a minute. By losing 1.3 times in the quality of the design, we can achieve, 10.7 times speedup in the Xilinx placement phase, and 2.5 times overall speedup in the Xilinx place-and-route phase.

Paper Details

Date Published: 6 October 2000
PDF: 12 pages
Proc. SPIE 4212, Reconfigurable Technology: FPGAs for Computing and Applications II, (6 October 2000); doi: 10.1117/12.402528
Show Author Affiliations
Kia Bazargan, Univ. of Minnesota/Twin Cities (United States)
Majid Sarrafzadeh, Northwestern Univ. (United States)

Published in SPIE Proceedings Vol. 4212:
Reconfigurable Technology: FPGAs for Computing and Applications II
John Schewel; Peter M. Athanas; Chris H. Dick; John T. McHenry, Editor(s)

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