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Proceedings Paper

Approach to constructing reconfigurable computer vision system
Author(s): Jianru Xue; Nanning Zheng; Xiaoling Wang; Yongping Zhang
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Paper Abstract

In this paper, we propose an approach to constructing reconfigurable vision system. We found that timely and efficient execution of early tasks can significantly enhance the performance of whole computer vision tasks, and abstract out a set of basic, computationally intensive stream operations that may be performed in parallel and embodies them in a series of specific front-end processors. These processors which based on FPGAs (Field programmable gate arrays) can be re-programmable to permit a range of different types of feature maps, such as edge detection & linking, image filtering. Front-end processors and a powerful DSP constitute a computing platform which can perform many CV tasks. Additionally we adopt the focus-of-attention technologies to reduce the I/O and computational demands by performing early vision processing only within a particular region of interest. Then we implement a multi-page, dual-ported image memory interface between the image input and computing platform (including front-end processors, DSP). Early vision features were loaded into banks of dual-ported image memory arrays, which are continually raster scan updated at high speed from the input image or video data stream. Moreover, the computing platform can be complete asynchronous, random access to the image data or any other early vision feature maps through the dual-ported memory banks. In this way, the computing platform resources can be properly allocated to a region of interest and decoupled from the task of dealing with a high speed serial raster scan input. Finally, we choose PCI Bus as the main channel between the PC and computing platform. Consequently, front-end processors' control registers and DSP's program memory were mapped into the PC's memory space, which provides user access to reconfigure the system at any time. We also present test result of a computer vision application based on the system.

Paper Details

Date Published: 6 October 2000
PDF: 11 pages
Proc. SPIE 4212, Reconfigurable Technology: FPGAs for Computing and Applications II, (6 October 2000); doi: 10.1117/12.402520
Show Author Affiliations
Jianru Xue, Xi'an Jiao Tong Univ. (China)
Nanning Zheng, Xi'an Jiao Tong Univ. (China)
Xiaoling Wang, Xi'an Jiao Tong Univ. (China)
Yongping Zhang, Xi'an Jiao Tong Univ. (China)


Published in SPIE Proceedings Vol. 4212:
Reconfigurable Technology: FPGAs for Computing and Applications II
John Schewel; Peter M. Athanas; Chris H. Dick; John T. McHenry, Editor(s)

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