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Proceedings Paper

High-performance reconfigurable constant coefficient multiplier implementations
Author(s): Philip B. James-Roxby; Brandon J. Blodget
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Paper Abstract

The use of dynamic reconfiguration appears extremely attractive for implementing adaptive processing algorithms. Often, the adaption involves updating look-up tables based on a parameter which can only be determined at run-time. For reasons of efficiency, these look-up tables are read-only to the rest of the circuitry. This paper compares the use of run-time reconfiguration and read-only look-up tables, with similar implementations using writable memories. The application under consideration is the multi-layer perceptron neural network. It is shown that the ROM based network is considerably simpler than the RAM based network, at the expense of a dramatically increased time to update the weights during training.

Paper Details

Date Published: 6 October 2000
PDF: 12 pages
Proc. SPIE 4212, Reconfigurable Technology: FPGAs for Computing and Applications II, (6 October 2000); doi: 10.1117/12.402519
Show Author Affiliations
Philip B. James-Roxby, Xilinx, Inc. (United States)
Brandon J. Blodget, Xilinx, Inc. (United States)


Published in SPIE Proceedings Vol. 4212:
Reconfigurable Technology: FPGAs for Computing and Applications II
John Schewel; Peter M. Athanas; Chris H. Dick; John T. McHenry, Editor(s)

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