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Proceedings Paper

DDGIPS: a general image processing system in robot vision
Author(s): Yuan Tian; Jun Ying; Xiuqing Ye; Weikang Gu
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Paper Abstract

Real-Time Image Processing is the key work in robot vision. With the limitation of the hardware technique, many algorithm-oriented firmware systems were designed in the past. But their architectures were not flexible enough to achieve a multi-algorithm development system. Because of the rapid development of microelectronics technique, many high performance DSP chips and high density FPGA chips have come to life, and this makes it possible to construct a more flexible architecture in real-time image processing system. In this paper, a Double DSP General Image Processing System (DDGIPS) is concerned. We try to construct a two-DSP-based FPGA-computational system with two TMS320C6201s. The TMS320C6x devices are fixed-point processors based on the advanced VLIW CPU, which has eight functional units, including two multipliers and six arithmetic logic units. These features make C6x a good candidate for a general purpose system. In our system, the two TMS320C6201s each has a local memory space, and they also have a shared system memory space which enables them to intercommunicate and exchange data efficiently. At the same time, they can be directly inter-connected in star-shaped architecture. All of these are under the control of a FPGA group. As the core of the system, FPGA plays a very important role: it takes charge of DPS control, DSP communication, memory space access arbitration and the communication between the system and the host machine. And taking advantage of reconfiguring FPGA, all of the interconnection between the two DSP or between DSP and FPGA can be changed. In this way, users can easily rebuild the real-time image processing system according to the data stream and the task of the application and gain great flexibility.

Paper Details

Date Published: 6 October 2000
PDF: 11 pages
Proc. SPIE 4212, Reconfigurable Technology: FPGAs for Computing and Applications II, (6 October 2000); doi: 10.1117/12.402515
Show Author Affiliations
Yuan Tian, Zhejiang Univ. (China)
Jun Ying, Zhejiang Univ. (China)
Xiuqing Ye, Zhejiang Univ. (China)
Weikang Gu, Zhejiang Univ. (China)


Published in SPIE Proceedings Vol. 4212:
Reconfigurable Technology: FPGAs for Computing and Applications II
John Schewel; Peter M. Athanas; Chris H. Dick; John T. McHenry, Editor(s)

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