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Proceedings Paper

Efficient resist edgebead removal for thick I-line resist coating application on TEL Mark 7 track sytem
Author(s): Quang Tran
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Paper Abstract

Photoresist coating process for IC device manufacturing requires correct target thickness, good uniformity and low defect density. For thick resist films used for Ion Implant, Top Metal layer and/or Pad masks, resist beads built up around the side edges and on top of wafer within 0-3 mm approximately from edges will need to be removed to eliminate defects during ion implantation and etch operations. The conventional method o f using solvent dispenses and optical exposure for edgebead removal does not necessarily solve this problem for resist thickness greater than 1.5 micron. For solvent EBR application, most resist track systems have both top and bottom dispenses nozzles for wafer edge cleaning. However, due to the high risk of unwanted EBR solvent splashes with top EBR nozzle onto wafer surface, which will destroy resist pattern resulting in yield loss, opt EBR solvent application is usually not used. Optical exposure system for wafer edges on the track equipment does not have enough power to completely expose thick photoresist film within a reasonable time for throughput requirement. Hence, the use of optical and backside EBRs only will result in incomplete resist edgebead removal. In this paper, we will describe a new top rinse nozzle design and a combined process of top and bottom EBRs to provide adequate and efficient resist removal around wafer edges for thick photoresist films. A low cost and easy modification to the existing standard to rinse nozzle fora TEL Mark 7 track system was done to provide efficient to solvent EBR application and to avoid solvent splash defects. The low angle to top rinse nozzle below 20 degrees was found to be important in reducing solvent droplet defects. The low angle of top rinse nozzle below 20 degrees was found to be important in reducing solvent droplet defects. Finally, a defect comparison study using KLS2132 will show a lower defect level for the modified top rinse nozzle than the standard one. Qualitative images of wafer edge cleanliness will be shown for resist thickness at 1.5, 1.8 and 2.5 microns using this new nozzle modification.

Paper Details

Date Published: 18 August 2000
PDF: 6 pages
Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); doi: 10.1117/12.395737
Show Author Affiliations
Quang Tran, Advanced Micro Devices, Inc. (United States)


Published in SPIE Proceedings Vol. 4181:
Challenges in Process Integration and Device Technology
David Burnett; Shin'ichiro Kimura; Bhanwar Singh, Editor(s)

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