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Proceedings Paper

Scaling considerations for MOSFET devices with 25-nm channel lengths
Author(s): Samar K. Saha
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Paper Abstract

A systematic simulation-based study on scaling gate oxide thickness and the source-drain extension junction dept of r25 nm MOSFET devices is presented. The target 25 nm MOSFETs were obtained from CMOS technologies with gate lengths 40, 50, and 60 nm and the corresponding source-drain extension junction depths of 14, 20, and 26 nm respectively. Each technology was separately optimized for each value of equivalent gate oxide thickness 1, 1.5 and 2 nm to achieve off-state leakage current <EQ 10 nA/micrometers for 25 nm devices. The simulate device characteristics show that for a target value of off-state leakage current, the magnitude of threshold voltage, sub-threshold slope, and the drain-induced barrier lowering increases while the magnitude of drive current decrease with the increase of gate oxide thickness. On the other hand, the variation in the magnitude of threshold voltage, sub-threshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insignificant within the range of source-drain extension junction depth, 14-26 nm, used in this study. It is also found that the gate delay for 25 nm devices increases significantly with the increase of source- drain extension junction depth. This study shows that the requirements for scaling gate oxide thickness and the source- drain extension junction depth for high performance 25 nm MOSFETs are <EQ 1.5 nm and 15 nm respectively.

Paper Details

Date Published: 18 August 2000
PDF: 10 pages
Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); doi: 10.1117/12.395731
Show Author Affiliations
Samar K. Saha, Cypress Semiconductor (United States)


Published in SPIE Proceedings Vol. 4181:
Challenges in Process Integration and Device Technology
David Burnett; Shin'ichiro Kimura; Bhanwar Singh, Editor(s)

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