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Proceedings Paper

Yield-limiting NMOSFET gate depletion in a deep submicrometer CMOS process
Author(s): Martin P. Karnett; Steven G. Qian; Todd Mitchell; Vijaya Subramaniam; Harlan Sur; Bradley J. Haby; Hunter B. Brugge
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Paper Abstract

Bitmap and electrical microprobe techniques were employed to detect and isolate NMOS gate depletion within the SRAM cells of our 0.20micrometers Complementary Poly CMOS process. This gate depletion problem led to a 3X drop-off in device drive current and about a 300mV increase in threshold voltage. These shifts in device performance produced massive circuit failures within memory circuits and zero yield at wafer probe. Experiments were performed towards conclusively identifying and resolving this gate depletion failure mechanism. Several process modifications were implemented towards eliminating the NMOS gate depletion problem without compromising our margin against PMOS boron penetration. These process improvements led to dramatic increases in probe yield.

Paper Details

Date Published: 18 August 2000
PDF: 9 pages
Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); doi: 10.1117/12.395729
Show Author Affiliations
Martin P. Karnett, Philips Semiconductors (United States)
Steven G. Qian, Philips Semiconductors (United States)
Todd Mitchell, Philips Semiconductors (United States)
Vijaya Subramaniam, Philips Semiconductors (United States)
Harlan Sur, Philips Semiconductors (United States)
Bradley J. Haby, Philips Semiconductors (United States)
Hunter B. Brugge, Philips Semiconductors (United States)


Published in SPIE Proceedings Vol. 4181:
Challenges in Process Integration and Device Technology
David Burnett; Shin'ichiro Kimura; Bhanwar Singh, Editor(s)

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