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Proceedings Paper

Isothermal test as a WLR monitor for Cu interconnects
Author(s): Amit P. Marathe; Van Pham; Jay Chan; Jorg-Oliver Weidner; Volker Heinig; Steffi Thierbach
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Paper Abstract

The need for higher interconnect current densities has been increasing rapidly for advanced integrated circuits. Cu interconnects have emerged as viable candidates to replace Aluminium due to the lower sheet resistivity and increased electro migration lifetime of Cu. Previously, we had reported the use of the isothermal test as a WLR monitor for detecting process defects such as voids in the Aluminium interconnects. This paper further extends the application of the isothermal test methodology for detecting and characterizing process defects in Cu interconnect technology. Package electro migration test are time consuming and may be impractical in detecting process defects in a timely manner. Isothermal test, on the other hand, can be effectively used as a fast WLR process monitor. This paper reports the influence of direction of test current as well as different types of test structures, such as a single level NIST structure and a via chain structure and a via chain structure, on the isothermal test results for Cu interconnects. The isothermal test data has been shown to be helpful in evaluating the location and severity of the process defects through a proper choice of test structures. Joule heating due to high current density is found to be the major driving force for the sensitivity of isothermal test failures. A good correlation is also seen with the package electro migration data. A simple wafer level isothermal test has thus been successfully demonstrated as a reliability tool for process monitoring in Cu VLSI interconnects.

Paper Details

Date Published: 18 August 2000
PDF: 8 pages
Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); doi: 10.1117/12.395727
Show Author Affiliations
Amit P. Marathe, Advanced Micro Devices, Inc. (United States)
Van Pham, Advanced Micro Devices, Inc. (United States)
Jay Chan, Advanced Micro Devices, Inc. (United States)
Jorg-Oliver Weidner, AMD Saxony Manufacturing GmbH (Germany)
Volker Heinig, AMD Saxony Manufacturing GmbH (Germany)
Steffi Thierbach, AMD Saxony Manufacturing GmbH (Germany)


Published in SPIE Proceedings Vol. 4181:
Challenges in Process Integration and Device Technology
David Burnett; Shin'ichiro Kimura; Bhanwar Singh, Editor(s)

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