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Proceedings Paper

Novel electrical alignment structure
Author(s): Todd Lukanc
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Paper Abstract

As geometries continue to shrink and the equipment is pushed closer to its true limits, overlay and other printing parameters become a larger part of the total budget. Overlay and CD measurements are sampled 'in line' to track and target tools. Adding these parameters to the electrically tested database along with sort data improves yield correlation and failure analysis both during development and in manufacturing. Typically electrical alignment structures such as a resistor divider work well for a few layers but are limited to layers connecting to resistor elements. This paper describes a novel resistor ladder structure that can measure alignment between any 2 conducting layers as well as measure tip pullback, layer to layer patterning impacts, and other characteristics in real device type layouts. Only mask generation and wafer printing capabilities limit the accuracy of the measurement.

Paper Details

Date Published: 18 August 2000
PDF: 6 pages
Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); doi: 10.1117/12.395717
Show Author Affiliations
Todd Lukanc, Advanced Micro Devices, Inc. (United States)


Published in SPIE Proceedings Vol. 4181:
Challenges in Process Integration and Device Technology
David Burnett; Shin'ichiro Kimura; Bhanwar Singh, Editor(s)

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