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Proceedings Paper

Advanced lithography kits: serifs and hammerhead
Author(s): Hang-Yip Liu; Steffen F. Schulze; Alan C. Thomas; Anne E. McGuire; Michael Cross
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Paper Abstract

Resolution enhancement techniques and higher NA exposure are employed to meet the lithography requirements imposed by aggressive shrinks to chip feature sizes. For certain critical levels, like storage and isolation patterning of DRAM devices, the capability to exactly reproduce the mask layout is limited. Severe corner rounding and line image shortening can occur. Such phenomena can be significant contributors to side effects like current leakage, inadequate retention time, stress, and perhaps yield loss. Our development work has shown that the use of Serif and Hammerhead structures can improve resolution printing. Moreover, better process latitude and CD control can be achieved. This paper gives an overview of these innovative techniques. It includes the consideration of different design layouts based on simulations, as well as mask making limitations e.g. mask inspection capability. The benefits of these techniques are discussed and illustrated with detailed lithographic performance data and SEM pictures.

Paper Details

Date Published: 18 August 2000
PDF: 12 pages
Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); doi: 10.1117/12.395715
Show Author Affiliations
Hang-Yip Liu, Infineon Technologies AG (United States)
Steffen F. Schulze, Infineon Technologies AG (United States)
Alan C. Thomas, IBM Microelectronics Div. (United States)
Anne E. McGuire, IBM Microelectronics Div. (United States)
Michael Cross, IBM Microelectronics Div. (United States)


Published in SPIE Proceedings Vol. 4181:
Challenges in Process Integration and Device Technology
David Burnett; Shin'ichiro Kimura; Bhanwar Singh, Editor(s)

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