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Proceedings Paper

High-frame-rate low-latency hardware-in-the-loop image generation: an illustration of the particle method and DIME
Author(s): Allan J. Cantle; Malachy Devlin; Eric Lord; Richard Chamberlain
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Paper Abstract

New computing architectures based on the DIME standard have been previously introduced which allow for processing of high frame rate imaging systems which may also need low latency capability, a common requirement for HWIL systems. This paper is presented in two sections: To achieve future realism in image generation systems for hardware-in-the-loop (HWIL) testing a significant increase in processing power is required, but additionally a suitable architecture is essential to provide low latency response on the data flow. Nallatech previously introduced DIME as a novel platform for HWIL systems which is capable of handling sub-frame latencies and greater than 100 Hz frame rates. We will demonstrate the system operating on traditional complex imaging problems, such as large convolution masks of 13 X 13 and also on new image generation techniques such as the particle method which is being developed by Matra British Aerospace Dynamics UK (MBDUK). MBDUK are proceeding on upgrading existing HWIL image generation systems for real-time particle models, to higher frame rates and increased complexity. Using Nallatech's latest DIME based architectures, models containing thousands of individual particles can be created at frame rates over 100 Hz and a resolution of 1024 X 1024 oversampled 4 times. This is possible because particle models exhibit high levels of parallelism ideal for exploiting the architecture of an FPGA. This paper will demonstrate the versatility of these particle models to create highly realistic signatures in terms of spatial dynamics and IR signature. Particle models are ideal for simulating dynamic objects such as flares, exhaust plumes, fires and explosions.

Paper Details

Date Published: 12 July 2000
PDF: 12 pages
Proc. SPIE 4027, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing V, (12 July 2000); doi: 10.1117/12.391680
Show Author Affiliations
Allan J. Cantle, Nallatech Ltd. (United Kingdom)
Malachy Devlin, Nallatech Ltd. (United Kingdom)
Eric Lord, Matra British Aerospace Dynamics Ltd. (United Kingdom)
Richard Chamberlain, Matra British Aerospace Dynamics Ltd. (United Kingdom)

Published in SPIE Proceedings Vol. 4027:
Technologies for Synthetic Environments: Hardware-in-the-Loop Testing V
Robert Lee Murrer, Editor(s)

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