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Proceedings Paper

Lossless layout compression for maskless lithography systems
Author(s): Vito Dai; Avideh Zakhor
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Paper Abstract

Future lithography systems must produce more dense chips with smaller feature sizes, while maintaining throughput comparable to today's optical lithography systems. This places stringent data-handling requirements on the design of any maskless lithography system. Today's optical lithography systems transfer one layer of data from the mask to the entire wafer in about sixty seconds. To achieve a similar throughput for a direct-write maskless lithography system with a pixel size of 25 nm, data rates of about 10 Tb/s are required. In this paper, we propose an architecture for delivering such a data rate to a parallel array of writers. In arriving at this architecture, we conclude that pixel domain compression schemes ar essential for delivering these high data rates. To achieve the desired compression ratios, we explore a number of binary lossless compression algorithms, and apply them to a variety of layers of typical circuits such as memory and control. The algorithms explored include the Joint Bi-Level Image Processing Group (JBIG), Ziv-Lempel (LZ77) as implemented by ZIP, as well as our own extension of Ziv-Lempel to two-dimensions. For all the layouts we tested, at least one of the above schemes achieves a compression ratio of 20 or larger, demonstrating the feasibility of the proposed system architecture.

Paper Details

Date Published: 21 July 2000
PDF: 11 pages
Proc. SPIE 3997, Emerging Lithographic Technologies IV, (21 July 2000); doi: 10.1117/12.390085
Show Author Affiliations
Vito Dai, Univ. of California/Berkeley (United States)
Avideh Zakhor, Univ. of California/Berkeley (United States)


Published in SPIE Proceedings Vol. 3997:
Emerging Lithographic Technologies IV
Elizabeth A. Dobisz, Editor(s)

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